1. Technical Field
The present disclosure relates to input output (IO) buffers and, more specifically, to an architecture and methodology for efficient usage of IO buffers that are optimized both in terms of area and performance.
2. Description of the Related Art
Rapid advances in semiconductor technology are driving the move of reducing device geometries and lower operating supply voltages. Several designs that operate reliably in an earlier device geometry or operating supply voltage fail to perform efficiently in the changed environment, resulting in the need for a redesign. This is especially true for IO buffers since these structures are required to interface to off-chip devices and drive significant loads. Standard drive level IO buffers do not provide an optimized solution in terms of area and performance.
FIG. 1(a) illustrates a known high voltage IO buffer and FIG. 1(b) illustrates a known low voltage IO buffer. It is observed that if the high voltage design is migrated to the lower supply voltage environment, it becomes necessary to increase the size of the buffer (height “H” micrometers (μm) and width “W” micrometers (μm)) since the device of the original size provides a significantly reduced drive at the low supply voltage. This change is implemented in the low-voltage design by increasing the width of the IO buffer (by “X” μm) and increasing the height of NMOS buffers by “a” μm, the height of the PMOS buffers by “b” μm and the height of the pre-driver by “c” μm. Since the overall height of the cell has to remain the same as before, these height increases results in a reduced available height for the logic area.